Xilinx CAN FD v2.0 Product Manual page 62

Table 2-44: CAN FD RX Message Space (Mailbox Buffers) (Cont'd)
Start
Name
Address
0x2F00 MRB0
0x2F04 MRB1
0x2F08 MRB2
0x2F0C MRB3
0x2F10-
MRB4-MRB47
0x2FBC
0x2FC0-
Reserved
0x2FFF
Notes:
1. Read from uninitialized memory location might return X or invalid data. Asserting a soft or hard reset does not
clear block RAM locations.
2. Message Buffer element resides in RX block RAM. Host should respect read access rules to avoid memory
collisions.
RB*-ID Register (Address Offset + 0x2100, 0x2148,...0x4100,...)
Description same as listed in
RB*-DLC Register (Address Offset + 0x2104, 0x214C,...0x4104,...)
Description same as listed in
RB*-DW Register (Address Offset + 0x2108, 0x210C,...0x2150, 0x2154,
...0x4108,...)
Description same as listed in
MRB* Register (Address Offset + 0x2F00, 0x2F04,...)
Description same as listed in
CAN FD v2.0
PG223 December 5, 2018
Access Description
See Acceptance Filter Mask
Register
Read, Write
Mask for mailbox buffer RB0.
See Acceptance Filter Mask
Register
Read, Write
Mask for mailbox buffer RB1.
See Acceptance Filter Mask
Register
Read, Write
Mask for mailbox buffer RB2.
See Acceptance Filter Mask
Register
Read, Write
Mask for mailbox buffer RB3.
See Acceptance Filter Mask
Register
Read, Write
Mask for mailbox buffer RB4
to RB47.
Reserved space. Write has no
–
effect. Read always returns 0.
Table 2-39, page 53.
Table 2-40, page 54.
Table 2-41, page 55.
Table 2-42, page 59.
www.xilinx.com
Chapter 2: Product Specification
Notes
MRB16 to MRB47 are valid
based on number of RX
buffers.
When RX buffers is chosen as
16 or 32, core does not allow
any write access outside the
respective address space and
read access returns 0.
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