Xilinx CAN FD v2.0 Product Manual page 32

Interrupt Enable TX Buffer Ready Request Served/Cleared (Address Offset +
0x0094)
Table 2-19: Interrupt Enable TX Buffer Ready Request Served/Cleared Register
Bits Name
31:8 ERRS31/ERRS8
7 ERRS7
6 ERRS6
5 ERRS5
4 ERRS4
3 ERRS3
2 ERRS2
1 ERRS1
0 ERRS0
TX Buffer Cancel Request (Address Offset + 0x0098)
Table 2-20: TX Buffer Cancel Request Register
Bits Name
R/W, Host writes 1
31:8 CR31/CR8
and core clears
7 CR7
6 CR6
5 CR5
4 CR4
3 CR3
2 CR2
R/W, Host writes 1
1 CR1
and core clears
0 CR0
Notes:
1. Host can set cancellation requests for multiple buffers in one write to this register.
CAN FD v2.0
PG223 December 5, 2018
Default
Access
Value
R/W 0
Note:
TX Buffer_0 Ready Req Served/Cleared Interrupt Enable
• 1 = Enables setting TXRRS bit in the ISR when RR0 bit in TRR
R/W 0 register clears.
• 0 = TXRRS bit in the ISR does not set if RR0 bit in TRR register
clears.
Default
Access
Value
Note:
0
TX Buffer_0 Cancel Request
This is cancellation request bit corresponds to RR0 bit in TRR
register.
Host writes 1 to indicate cancellation request of corresponding
buffer ready request (that is, RR0 bit in TRR register). The core
clears this bit when cancellation request is completed.
Host writes to this bit are ignored if CR0 is 1 or RR0 bit of TRR
register is 0.
If the buffer is already locked for transmission by Transfer Layer
0
then cancellation is performed at the end of transmission cycle
irrespective whether frame transmitted successfully or failed.
That is, if message is failed due to arbitration loss or any error,
then the message is cancelled (no retransmission attempt) and
cancellation request is cleared. Along with RR0 bit this is
cleared.
If message is transmitted successfully, then RR0 bit clears and
cancellation request is cleared anyway.
Note:
cancellation consideration is postponed till it is over.
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Description
These bits exist based on the number of TX buffers.
Description
These bits exist based on the number of TX buffers.
If internal buffer scheduling round is in progress, then
Chapter 2: Product Specification
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