Xilinx CAN FD v2.0 Product Manual page 73

5. After reading the message, write the FSR register by setting the respective IRI bit to 1.
This enables the core to increment the respective Read Index field by +1 and updates
the corresponding Fill Level in the FSR register. If Fill level is 0, setting IRI bit has no
effect.
6. Repeat steps 3 through 5 until all messages are read from either RX FIFO-0 or RX
FIFO-01.
RX – Core Actions
1. When a message is successfully received, the core writes the timestamp and matched
filtered index field of the received message element.
2. The CAN FD increments the Fill Level of its respective RX FIFO in the FSR register by 1
after every successful receive (without error and message passes filtering scheme).
3. The Fill Level is also updated by the core after the Host writes the IRI bit of respective RX
FIFO in the FSR register.
Filtering
Each acceptance filter pair has an Acceptance Filter Mask register and an Acceptance Filter
ID register. Each filter pair a has corresponding UAF bit to control enable/disable.
Filtering when RX FIFO-1 is absent or disabled
Filtering is performed in the following sequence:
1. The incoming Identifier is masked with the bits in the Acceptance Filter Mask register.
2. The Filter ID register is also masked with the bits in the Acceptance Filter Mask register.
3. Both resulting values are compared.
4. If both these values are equal, then the message is stored in RX FIFO-0.
5. Filtering is processed by each of the defined filters. If the incoming identifier passes
through any filter, the message is stored in RX FIFO-0.
RX FIFO-1 can be disabled (that is, stop routing messages to RX FIFO-1) by programming
Note:
RXFP as 'd31 (in RX FIFO Watermark register). See Register description for more detail.
Filtering when RX FIFO-1 is enabled
In this case, the RXFP field (in the RX FIFO Watermark register) along with the Filter
(Control) register determines whether received messages are stored in RX FIFO-0 or RX
FIFO-1. In this case, the RXFP field must be less than 'd31.
1. The incoming Identifier is masked with the bits in the Acceptance Filter Mask register.
2. The Filter ID register is also masked with the bits in the Acceptance Filter Mask register.
CAN FD v2.0
PG223 December 5, 2018 www.xilinx.com
Chapter 3: Designing with the Core
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