Xilinx CAN FD v2.0 Product Manual page 42

Table 2-29: RX FIFO Watermark Register (Cont'd)
Bits Name
5:0 RXFWM
Notes:
1. This register space is reserved for RX Mailbox buffer mode. Write has no effect and read returns 0.
CAN FD TX Message Space Register Descriptions
Table 2-30: CAN FD TX Message Space
Start
Name
Address
0x0100 TB0-ID
0x0104 TB0-DLC
0x0108 TB0-DW0
0x010C TB0-DW1
0x0110 TB0-DW2
0x0114 TB0-DW3
0x0118 TB0-DW4
0x011C TB0-DW5
0x0120 TB0-DW6
0x0124 TB0-DW7
0x0128 TB0-DW8
0x012C TB0-DW9
0x0130 TB0-DW10
0x0134 TB0-DW11
0x0138 TB0-DW12
0x013C TB0-DW13
0x0140 TB0-DW14
0x0144 TB0-DW15
CAN FD v2.0
PG223 December 5, 2018
Access Default
Value
RX FIFO-0 Full Watermark.
RX FIFO-0 generates FULL interrupt based on the value
programmed in this field.
Set it within (1-63) range.
R/W 0xf
The RX FIFO-0 Full Watermark interrupt in the ISR register
continues to assert as long as the RX FIFO-0 Fill Level is above
RX FIFO-0 Full watermark.
This field can be written to only when CEN bit in SRR is 0.
Access
TB ID Register
TB0 Message space inside
Read, Write
memory mapped TX block
RAM.
Read, Write TB DLC Register
Read, Write TB DW0 Register
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write See TB DW0 Register
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
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Chapter 2: Product Specification
Description
Description
Only required DW locations
needs to be written as per
FDF and DLC field for a given
message.
Notes
42
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