Xilinx CAN FD v2.0 Product Manual page 23

Table 2-12: Interrupt Status Register (Cont'd)
Access Default
Bits Name
29:24 RXBOFLW_BI
23:18 RXLRM_BI
17 RXMNF
RXBOFLW/
16
RXFWMFLL_1
RXRBF/
15
RXFOFLW_1
14 TXCRS
CAN FD v2.0
PG223 December 5, 2018
Value
RX Buffer Index for Overflow Interrupt (Mailbox mode).
Gives RX Buffer index for which overflow event is generated. This field
is automatically cleared to default if RXBOFLW bit is cleared in this
register. In case more than one overflow event happens (before Host
R 0
could clear RXBOFLW), RXBOFLW_BI shows the overflow index for the
last event. This field has meaning only if the overflow interrupt
RXBOFLW bit is set. This field is also cleared at hard/soft reset or when
a 0 is written to the CEN bit in the SRR.
RX Buffer Index for Last Received Message (Mailbox mode).
Gives the RX Buffer index for the last received message. This field has
R 0
meaning only if the RXOK bit is set in this register. This field is cleared
at hard/soft reset or when a 0 is written to the CEN bit in the SRR.
RX Match Not Finished.
• 1 = Indicates that Match process did not finish until the start of sixth
R 0
bit in EOF field and frame was discarded.
This bit can be cleared by writing to the respective bit in the ICR.
RX Buffer Overflow Interrupt (Mailbox mode).
• 1 = Indicates that a message has been lost due to buffer overflow
condition. Buffer index is captured in RXBOFLW_BI field.
This bit can be cleared by writing to the respective bit in the ICR.
RX FIFO 1 Watermark Full Interrupt (Sequential/FIFO Mode).
R 0
• 1 = Indicates that RX FIFO-1 is full based on watermark
programming.
This interrupt is only available when RX FIFO-1 is enabled.
Note:
The interrupt continues to assert as long as the RX FIFO-1 Fill Level is
above the RX FIFO-1 Full watermark.
This bit can be cleared by writing to the respective bit in the ICR.
RX Buffer Full Interrupt (Mailbox mode).
• 1 = Indicates that a receive buffer has received a message and
become full.
This bit can be cleared by writing to the respective bit in the ICR.
RX FIFO-1 Overflow Interrupt (Sequential/FIFO Mode).
R 0
• 1 = Indicates that a message has been lost. This condition occurs
when a new message with ID matching to Receive FIFO 1 is received
and the Receive FIFO 1 is full.
This interrupt is only available when RX FIFO-1 is enabled.
Note:
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
TX Cancellation Request Served Interrupt.
R 0 • 1 = Indicates that a cancellation request was cleared.
This bit can be cleared by writing to the respective bit in the ICR.
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Chapter 2: Product Specification
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