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Table 3-1: CAN FD Core Operating Mode Transitions (Cont'd)
SRR
Register
MSR Register Bits
System
Bits
(Hard)
Reset
SRST
(SW
CEN LBACK SLEEP SNOOP Config
Reset)
0
1
0
1
Notes:
1. X-Control bit don't care. Status bit does not mean anything.
2. Transition to Bus-Off state depends on Transmit Error Count value as per standard specification. Recovery from Bus-Off state
depends on SBR and ABR bit settings in the MSR register (as per respective bit behavior description). Bus-Off Recovery can
be tracked through status bit BSFR_CONFIG in SR register and REC field in ECR register. Entry and exit from Bus-Off state can
also generate interrupt.
3. Transition to CAN FD Protocol Exception State (PEE) depends on the DPEE bit in MSR register. The core enters and exits PEE
state as per ISO standard specification and this is reflected by status bit PEE_CONFIG in the SR register. Entry to PEE state
can also generate interrupt.
Configuration Mode
The core enters Configuration mode, irrespective of the operation mode, when any of the
following actions are performed:
•
Writing a 0 to the CEN bit in the SRR register.
•
Writing a 1 to the SRST bit in the SRR register.
•
Driving a 0 on the Reset input.
After reset, the core exits Configuration mode after the CEN bit is set and 11 consecutive
nominal recessive bits are seen on the CAN bus.
CAN FD v2.0
PG223 December 5, 2018
BSFR_
Config
X
X
X
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
X
0
0
0
X
X
0
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Chapter 3: Designing with the Core
SR (Status) Register Bits
PEE_
LBACK SLEEP NORMAL SNOOP
Config
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
1
0
0
Operation Mode
0
0
Configuration
1
0
Normal
1
1
Snoop
0
0
Sleep
0
0
Loopback
Bus-Off
X
0
(2)
Recovery
(3)
X
X
PEE
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