Xilinx CAN FD v2.0 Product Manual page 25

Table 2-12: Interrupt Status Register (Cont'd)
Access Default
Bits Name
3 BSFRD
2 PEE
1 TXOK(1)
0 ARBLST
Notes:
1. In Loopback mode, both TXOK and RXOK bits are set. The RXOK bit is set before the TXOK bit.
Interrupt Enable Register (Address Offset + 0x0020)
The Interrupt Enable register (IER) bits are used to enable interrupt generation when
respective event happens.
Table 2-13: Interrupt Enable Register
Bits Name
31 ETXEWMFLL
30 ETXEOFLW
17 ERXMNF
CAN FD v2.0
PG223 December 5, 2018
Value
Bus-Off Recovery Done Interrupt.
• 1 = Indicates that the core recovered from Bus-Off state.
R 0
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
Protocol Exception Event Interrupt.
• 1 = Indicates that the core (CAN FD receiver) has detected PEE event.
R 0
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
Transmission Successful Interrupt.
• 1 = Indicates that a message was transmitted successfully.
R 0
This bit can be cleared by writing to the respective bit in the ICR. This
bit is also cleared when a 0 is written to the CEN bit in the SRR.
Arbitration Lost Interrupt.
• 1 = Indicates that arbitration was lost during message transmission.
R 0
This bit can be cleared by writing to the respective bit in the ICR. This
bit is also cleared when a 0 is written to the CEN bit in the SRR.
Default
Access
Value
TX Event FIFO Watermark Full Interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if TXEWMFLL bit in the ISR is set.
• 0 = Disables interrupt generation if TXEWMFLL bit in the ISR is set.
TX Event FIFO Overflow Interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if TXEOFLW bit in the ISR is set.
• 0 = Disables interrupt generation if TXEOFLW bit in the ISR is set.
RX Match Not Finished interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if RXMNF bit in the ISR is set.
• 0 = Disables interrupt generation if RXMNF bit in the ISR is set.
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Chapter 2: Product Specification
Description
Description
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