Xilinx CAN FD v2.0 Product Manual page 69

Register Configuration Sequence
The following are steps to configure the CAN FD when the core is powered on or after
system or software reset.
1. Choose the operating mode:
Normal – Write 0s to the LBACK, SNOOP, and SLEEP bits in the MSR. Write required
°
value for BRS and DAR fields in the MSR register.
Sleep – Write 1 to the SLEEP bit in the MSR and 0 to the LBACK and SNOOP bits in
°
the MSR. Write required value for BRS and DAR fields in the MSR register.
Loopback – Write 1 to the LBACK bit in the MSR and 0 to the SLEEP and SNOOP
°
bits in the MSR. Write required value for BRS fields in the MSR register.
Snoop – Write 1 to the SNOOP bit in the MSR and 0 to the LBACK and SLEEP bits in
°
the MSR register.
2. Configure the Transfer Layer Configuration registers.
For proper operations, ensure that all CAN FD nodes in the network are programmed to
IMPORTANT:
have the same Arbitration Phase bit rate, Data Phase bit rate, Arbitration Phase sample point position,
and Data Phase sample point position.
Program the Arbitration Phase (Nominal) Baud Rate Prescaler register and
°
Arbitration Phase (Nominal) Bit Timing register with the value calculated for the
particular arbitration phase bit rate.
Program the Data Phase Baud Rate Prescaler register and Data Phase Bit Timing
°
register with the value to achieve desired data phase bit rate.
- The Data Phase Bit Timing register also contains TDC control fields.
The bit rate configured for the data phase must be higher than or equal to the bit rate
Note:
configured for the arbitration phase. The Transfer Layer Configuration Registers can be
changed only when the CEN bit in the SRR Register is 0.
Step 3 is only for Receive Sequential/FIFO mode.
IMPORTANT:
3. Configure the Acceptance Filter registers (AFR, AFMR, AFIR) to the following:
Write a 0 to the UAF bit in the register corresponding to the Acceptance Filter Mask
°
and the ID register pair to be configured.
Write the required mask information to the Acceptance Filter Mask register.
°
Write required ID information to the Acceptance Filter ID register.
°
Write 1 to the UAF bit corresponding to the Acceptance Filter Mask and ID register
°
pair.
Repeat the steps for each Acceptance Filter Mask and ID register pair.
°
CAN FD v2.0
PG223 December 5, 2018 www.xilinx.com
Chapter 3: Designing with the Core
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