Debug Tools - Xilinx CAN FD v2.0 Product Manual

Debug Tools

There are many tools available to address CAN FD design issues. It is important to know
which tools are useful for debugging various situations.
Vivado Design Suite Debug Feature
®
The Vivado Design Suite debug feature inserts logic analyzer and virtual I/O cores directly
into your design. The debug feature also allows you to set trigger conditions to capture
application and integrated block port signals in hardware. Captured signals can then be
analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a
design running in Xilinx devices.
The Vivado logic analyzer is used with the logic debug LogiCORE IP cores, including:
• ILA 2.0 (and later versions)
• VIO 2.0 (and later versions)
See the Vivado Design Suite User Guide: Programming and Debugging (UG908)
Hardware Debug
These are some common issues that might be encountered.
1. The desired baud rate is not seen on the TX/RX lines.
Action: Ensure that the desired values are written to the BRPR and BTR registers. The
actual value is one more than the value written into the registers.
2. The core is not achieving CONFIG state after it is enabled.
Action: After the occurrence of 11 consecutive recessive bits, the CAN FD core clears the
CONFIG bit and sets the appropriate bit in the Status register. Ensure that 11
consecutive recessive bits are seen by the core.
3. The core is enabled and the desired BRPR/BTR values are written but the lines are not
toggling.
Action: Ensure that the can_clk port is connected to the desired clock source.
4. CAN FD core is generating various frame errors in the network with other nodes when
CAN FD frames are used.
CAN FD v2.0
PG223 December 5, 2018 www.xilinx.com
Appendix C: Debugging
[Ref 12].
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