Xilinx CAN FD v2.0 Product Manual page 31

Table 2-17: Data Phase Bit Timing Register (Cont'd)
Access Default
Bits Name
7:5 Reserved
4:0 DP_TS1[4:0] R/W
TX Buffer Ready Request Register (Address Offset + 0x0090)
Table 2-18: TX Buffer Ready Request Register
Bits Name
R/W, Host writes 1
31:8 RR31/RR8
and core clears
7 RR7
6 RR6
5 RR5
4 RR4
3 RR3
R/W, Host writes 1
2 RR2
and core clears
1 RR1
0 RR0
Notes:
1. Host can set transmission requests for multiple buffers in one write to this register.
2. Write with any value to this register triggers buffer scheduler to redo the scheduling round to find winning buffer
(exceptions: when Transfer Layer is in 3-bit Intermission space without locked buffer or if previous scheduling round is
already running. In those situation, buffer scheduler trigger is postponed till the event is over).
Unnecessary writes to this register might reduce core throughput on the CAN bus. Ensure
IMPORTANT:
this register is written only when it is required.
CAN FD v2.0
PG223 December 5, 2018
Value
– 0 Reserved
Data Phase Time Segment 1
Indicates the Sum of Propagation Segment and Phase Segment 1 as
specified in the CAN FD standard for Data Bit Timing.
0
The actual value is one more than the value written to the register.
This bit can be written only when CEN bit in SRR is 0.
Default
Access
Value
0
0
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Chapter 2: Product Specification
Description
Description
These bits exist based on the number of TX buffers.
Note:
TX Buffer_0 Ready Request
This is control bit corresponds to TB0 message in TX block
RAM.
Host writes 1 to indicate buffer is ready for transmission.
Core clears this bit when:
• Buffer transmission is completed on CAN Bus
• If core is in DAR mode, then after one transmission
attempt on the CAN bus [either successful or
unsuccessful (that is, arbitration lost or error)]
• If message is cancelled due to cancellation request
• Any combination of the above three.
Host writes to this bit are ignored when this bit is 1.
This register remains in reset when SNOOP mode is
Note:
enabled.
31
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