Xilinx CAN FD v2.0 Product Manual page 88

Test Bench
This chapter contains information about the test bench provided in the Vivado
Suite. Figure 6-1
bench generates a 200 MHz clock and drives an initial reset to the example design.
X-Ref Target - Figure 6-1
<component_name>_tb
CAN FD v2.0
PG223 December 5, 2018
shows the test bench for the CAN FD example design. The top-level test
Clock Reset
Generation
Test Status
Checker
Figure 6-1: Test Bench
www.xilinx.com
clk_in1_p
clk_in1_n
reset
Example Design
done
status
Chapter 6
®
Design
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