Xilinx CAN FD v2.0 Product Manual page 50

Table 2-36: TXE FIFO TB DLC Register (Cont'd)
Bits Name
25:24 ET
23:16 MM
15:0 Timestamp
CAN FD RX Message Space (Sequential/FIFO Buffers-RX FIFO-0)
Register Descriptions
Table 2-37: CAN FD RX Message Space (Sequential/FIFO Buffers - RX FIFO-0)
Start
Name
Address
0x2100 RB0-ID
0x2104 RB0-DLC
0x2108 RB0-DW0
CAN FD v2.0
PG223 December 5, 2018
Control/ Default
Status Value
Event Type.
• 11 -> Transmitted.
• 01 -> Transmitted in spite of cancellation request or DAR
Status N/A
mode transmissions.
• 00 -> Reserved.
• 10 -> Reserved.
Message Marker.
Written by CPU during TX Buffer configuration. Copied into
Status N/A
Tx Event FIFO element for identification of TX message
status.
Timestamp captured after SOF bit. This is written by the core
Status N/A
for status purpose for successfully transmitted message.
Access
64 Message Deep Sequential (FIFO) Buffer Space
RB ID Register
RB0 Message space inside
Read Only
memory mapped RX block
RAM.
Read Only RB DLC Register
Read Only RB DW0 Register
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Chapter 2: Product Specification
Description
Description
Only required DW locations
needs to be read as per FDF
and DLC field for a given
message.
IMPORTANT:
unintended writes are done
from Host interface to RX
block RAM message space
(core does not block writes to
RX block RAM message
space).
Notes
Ensure no
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