Upgrading In The Vivado Design Suite - Xilinx CAN FD v2.0 Product Manual

Upgrading
This appendix contains information about upgrading to a recent version of the core.

Upgrading in the Vivado Design Suite

Parameter Changes
On the Customize IP screen, the Processor Interface parameter allows you to determine if
the AXI4-Lite or APB interface communicates with the processor.
When Sequential RX mode is selected, you can use the Enable RX FIFO-1 parameter to
determine if the IP should have a second RX FIFO. The RX FIFO-0 Depth and RX FIFO-1
Depth parameters define the depths of RX Buffer FIFO-0 and RX Buffer FIFO-1 respectively.
Port Changes
See Table B-1 for a list of new and changed ports in v2.0.
.
Table B-1: New Ports
Port Name
can_clk_x2
apb_clk
apb_resetn
apb_pwdata[31:0]
apb_paddr[14:0]
apb_pwrite
apb_psel
apb_penable
apb_prdata[31:0]
apb_pready
apb_perror
CAN FD v2.0
PG223 December 5, 2018
See Port Descriptions for details.
See Port Descriptions for details.
See Port Descriptions for details.
See Port Descriptions for details.
See Port Descriptions for details.
See Port Descriptions for details.
See Port Descriptions for details.
See Port Descriptions for details.
See Port Descriptions for details.
See Port Descriptions for details.
See Port Descriptions for details.
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Appendix B
Notes
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