Xilinx CAN FD v2.0 Product Manual page 52

CAN FD RX Message Space (Sequential/FIFO Buffers-RX FIFO-1)
Register Descriptions
Table 2-38: CAN FD RX Message Space (Sequential/FIFO Buffers - RX FIFO-1)
Start
Name
Address
0x4100 RB0_1-ID
0x4104 RB0_1-DLC
0x4108 RB0_1-DW0
0x410C RB0_1-DW1
0x4110 RB0_1-DW2
0x4114 RB0_1-DW3
0x4118 RB0_1-DW4
0x411C RB0_1-DW5
0x4120 RB0_1-DW6
0x4124 RB0_1-DW7
0x4128 RB0_1-DW8
0x412C RB0_1-DW9
0x4130 RB0_1-DW10
0x4134 RB0_1-DW11
0x4138 RB0_1-DW12
0x413C RB0_1-DW13
0x4140 RB0_1-DW14
0x4144 RB0_1-DW15
CAN FD v2.0
PG223 December 5, 2018
Access
64 Message Deep Sequential (FIFO) Buffer Space
RB ID Register
RB0 Message space inside
Read Only
memory mapped RX block
RAM.
Read Only RB DLC Register
Read Only RB DW0 Register
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only See RB DW0 Register
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
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Chapter 2: Product Specification
Description
Only required DW locations
needs to be read as per FDF
and DLC field for a given
message.
IMPORTANT:
unintended writes are done
from Host interface to RX
block RAM message space
(core does not block writes
to RX block RAM message
space).
Notes
Ensure no
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