Xilinx CAN FD v2.0 Product Manual page 76

2. The CAN FD changes the buffer status to Full when the message is received without
errors and is timestamped. In case of errors (for example, CRC error), the buffer status
remains Active.
3. If enabled through IERBF and IER, the RXRBF bit is set in the ISR register (when the core
changes the RCS buffer status to Full) and interrupt is generated.
Notes
The CAN FD accesses the RX block RAM message element space of a buffer based on the
buffer status.
a. Active: Read access for ID and Mask. Write access for the received message. Read
and Write access for the timestamp.
b. Full: Read access for ID and Mask to find overflow condition.
The host should respect access rules to avoid memory collisions. For example,
a. If the buffer status is Active, do not access the corresponding block RAM space.
b. If the buffer status is Full, do not change the respective ID and Mask.
Because ID and Mask registers are in the block RAM, asserting a software reset or system
IMPORTANT:
reset does not clear these register contents. Host has to properly initialize them before use.
Notes on the ID Match Process
1. It is expected that the AXI4-Lite/APB clock frequency is sufficiently fast that the match
process finishes before the frame reception is completed on the CAN bus.
2. If the core is not able to complete the match process before the EOF sixth bit, it sets the
RX MNF bit in the ISR register.
3. The RX Mailbox control logic in the Object layer waits for the Transfer layer to signal
RXOK (EOF sixth bit) before setting the corresponding RCSx(i) bit to indicate that the RX
Buffer is full.
4. It is possible for the CAN bus to encounter an error after the Data field of the current
frame (the sixth bit of the EOF field). In this situation, the Mailbox control logic does not
set the RCSx(i) bit to indicate that the RX Buffer is full. The RX block RAM matched
element might show a partial or full data update.
5. The ID received with the message is written into the ID field of the Mailbox buffer.
Example 1:
Host programmed ID & Mask:
ID reg : 0x1234_5678
Mask reg : 0xFFFF_FF00
Incoming IDs 0x1234_56xx will match this mailbox buffer.
CAN FD v2.0
PG223 December 5, 2018 www.xilinx.com
Chapter 3: Designing with the Core
Send Feedback
76