Xilinx CAN FD v2.0 Product Manual page 74

3. Both resulting values are compared.
4. If both these values are equal and matched filter index is less than equal to the RXFP
field, the message is stored in RX FIFO-0.
5. Else, if both these values are equal and the matched filter index is greater than the RXFP
field, the message is stored in RX FIFO-1.
The ID match process is a sequential process. It starts from the lowest enabled filter and
stops at the first match. Therefore, if the incoming message fulfills condition 4 but RX
FIFO-0 is full, the message is dropped (irrespective of RX FIFO-1 status) and RX FIFO-0
overflow is indicated.
Similarly, if incoming message fulfills condition 5 but RX FIFO-1 is full, the message is
dropped (irrespective of RX FIFO-0 status) and RX FIFO-1 overflow is indicated. See
Figure 2-1 to Figure 2-4, page 58
If all UAF bits are set to 0, the received messages are not stored in any RX FIFO.
Note:
a. Filter pair registers are stored in the block RAM memory. Host has to ensure each
used filter pair is properly initialized. Asserting a software reset or system reset does
not clear these register contents.
b. Host must initialize/update/change filter pair only when the corresponding UAF is 0.
Ensure proper programming of the IDE bit for standard and extended frames in the Mask
IMPORTANT:
register and ID register. If you set the IDE bit in the Mask register as 0, it is considered to be a standard
frame ID check only and therefore if Standard ID bits of the incoming message match with the
respective bits of Filter ID (after applying Mask register bits), the message is stored.
Reception (Mailbox Mode)
Each receive message element in the RX block RAM has two bits. The HCBx bit gives the
Host control to make a Buffer Active or Inactive and CSBx bit gives the core status (Buffer
is Full). Together, these two bits give the buffer status as Inactive, Active, Full, or Invalid.
These bits are described in detail in the Receive Buffer Control Status (RCS) registers. Each
receive message element also has one ID Mask Register in the RX block RAM.
CAN FD v2.0
PG223 December 5, 2018
for details.
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Chapter 3: Designing with the Core
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