Xilinx CAN FD v2.0 Product Manual page 66

Configuration Mode Characteristics
The CAN FD core has the following Configuration mode characteristics:
• The Controller loses synchronization with the CAN bus and drives a constant recessive
bit on the TX line.
• The Error Counter register is reset.
• The Error Status register is reset.
• The BTR and BRPR registers can be modified.
• The CONFIG bit in the status register is 1.
• The core does not receive any new messages.
• The core does not transmit any messages.
• All configuration registers are accessible.
• If there are messages pending for transmission when CEN is written 0, they are
preserved (unless cancelled) and transmitted when normal operation is resumed.
• Message cancellation is permitted.
• New messages can be added for transmission (provided the SNOOP bit is not set in the
MSR register).
• If there are new received messages available, they are preserved until the host reads
them.
• The Interrupt Status register bits ARBLST, TXOK, RXOK, RXOFLW, RXOFLW_1, ERROR,
BSOFF, SLP, and WKUP are cleared.
• Interrupt Status register bits TXTRS and TXCRS can be set due to cancellation.
• Interrupts are generated if the corresponding bits in the IER are 1.
• When in Configuration mode, the Controller stays in this mode until the CEN bit in the
SRR register is set to 1.
• After the CEN bit is set to 1, the Controller waits for a sequence of 11 nominal recessive
bits before exiting Configuration mode.
• CAN FD enters Normal, Loopback, Snoop or Sleep modes from Configuration mode,
depending on the LBACK, SNOOP, and SLEEP bits in the MSR Register.
CAN FD v2.0
PG223 December 5, 2018 www.xilinx.com
Chapter 3: Designing with the Core
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