Xilinx CAN FD v2.0 Product Manual page 37

Table 2-26: Interrupt Enable RX Buffer Full Register 1 (Cont'd)
Bits Name
0 ERBF32
Notes:
1. This register space is reserved for RX Sequential/FIFO mode or when the number of RX mailbox buffers are 16 or
32. When reserved, write has no effect and read returns 0.
Acceptance Filter (Control) Register (Address Offset + 0x00E0)
In RX Sequential/FIFO buffer mode, the Acceptance Filter (Control) register (AFR) defines
which acceptance filters to use. Each Acceptance Filter ID register (AFIR) and Acceptance
Filter Mask register (AFMR) pair is associated with a UAF bit.
• When the UAF bit is 1, the corresponding acceptance filter pair is used for acceptance
filtering. When the UAF bit is 0, the corresponding acceptance filter pair is not used for
acceptance filtering.
• To modify an acceptance filter pair in Normal mode, the corresponding UAF bit in this
register must be set to 0.
• After the acceptance filter is modified, the corresponding UAF bit must be set to 1.
• If all UAF bits are set to 0, the received messages are not stored in the RX Sequential/
FIFO buffers.
• If the UAF bits are changed from a 1 to 0 during reception of a message, then that
message might or might not be stored.
Table 2-27: Acceptance Filter (Control) Register
Bits Name
31 UAF31
30 UAF30
29 UAF29
28 UAF28
27 UAF27
CAN FD v2.0
PG223 December 5, 2018
Access Default
Value
RX Buffer_32 Full Interrupt Enable
• 1 = Enables setting RXBFL bit in the ISR when RX Buffer
R/W 0 32 becomes Full.
• 0 = RXBFL bit in the ISR does not set if RX Buffer 32
becomes Full.
Default
Access
Value
Use Acceptance Filter Mask Pair 31.
R/W 0
Description same as UAF0.
Use Acceptance Filter Mask Pair 30.
R/W 0
Description same as UAF0.
Use Acceptance Filter Mask Pair 29.
R/W 0
Description same as UAF0.
Use Acceptance Filter Mask Pair 28.
R/W 0
Description same as UAF0.
Use Acceptance Filter Mask Pair 27.
R/W 0
Description same as UAF0.
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Chapter 2: Product Specification
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