Xilinx CAN FD v2.0 Product Manual page 18

Arbitration Phase (Nominal) Bit Timing Register (Address Offset + 0x000C)
Table 2-8: Arbitration Phase Bit Register
Bits Name
31:23 Reserved
22:16 SJW[6:0]
15 Reserved
14:8 TS2[6:0]
7:0 TS1[7:0]
Error Count Register (Address Offset + 0x0010)
The ECR is a read-only register. Writes to the ECR have no effect. The values of the error
counters in the register reflect the values of the transmit and receive error counters in the
core. The following conditions reset the Transmit and Receive Error counters:
• When 1 is written to the SRST bit in the SRR.
• When 0 is written to the CEN bit in the SRR.
• When the core enters Bus-Off state.
• During Bus-Off recovery until the core enters Error Active state (after 128 occurrences
of 11 consecutive recessive bits).
When in Bus-Off recovery, the Receive Error counter is advanced/incremented by 1 when
IMPORTANT:
a sequence of 11 consecutive nominal recessive bits is seen.
In SNOOP mode, error counters are disabled and cleared to 0. Reads to the Error Counter
Note:
register return 0.
CAN FD v2.0
PG223 December 5, 2018
Access Default
Value
– 0 Reserved.
Synchronization Jump Width.
Indicates the Synchronization Jump Width as specified in the
standard for Nominal Bit Timing.
R/W 0
The actual value is one more than the value written to the register.
These bits can be written only when the CEN bit in SRR is 0.
– 0 Reserved.
Time Segment 2
Indicates the Phase Segment 2 as specified in the standard for
Nominal Bit Timing.
R/W 0
The actual value is one more than the value written to the register.
These bits can be written only when the CEN bit in SRR is 0.
Time Segment 1
Indicates the Sum of Propagation Segment and Phase Segment 1
as specified in the standard for Nominal Bit Timing.
R/W 0
The actual value is one more than the value written to the register.
These bits can be written only when the CEN bit in SRR is 0.
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Chapter 2: Product Specification
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