Xilinx CAN FD v2.0 Product Manual page 70

If you want to enable RX FIFO-1, you need to arrange the Filter Mask and ID register
°
as per the requirement. The RXFP field in RX FIFO Watermark register also needs to
be set accordingly to a value less than 'd31.
Step #4 is only for Receive Mailbox mode.
IMPORTANT:
4. Configure the Mask registers (MRB) for RX Mailbox buffers. Configure the RB-ID register
of the respective buffer and set the control bit in the RCS register to make the buffer
status Active.
5. Program the Interrupt Enable registers as per requirements.
6. Enable protocol controller by writing a 1 to the CEN bit in the SRR register.
After the occurrence of 11 consecutive recessive bits, the CAN FD clears the CONFIG bit
in the Status register to 0 and sets the appropriate Mode Status bit in the Status register.
RECOMMENDED:
so that operation starts afresh. Also, the LBACK, SLEEP, and SNOOP bits should never be set to 1 at the
same time.
Message Transmission, Cancellation, and Reception
Transmission
All messages written in the TX buffer must follow the required message format for the ID,
DLC, and DW fields described earlier. Each RR bit of the TX Buffer Ready Request (TRR)
register corresponds to a message element in the TX block RAM.
TX – Host Actions
1. Poll the TRR register to check current pending transmission requests.
2. If all bits of the TRR register are set, a new transmission request can only be added if:
a. One or more buffer transmission requests are cancelled, or
b. One or more buffer transmissions complete.
3. If one or more bits of the TRR register are unset/clear, a new transmission request can be
added as follows:
a. First, prepare one or more message elements in the TX block RAM (by writing valid
ID, DLC, and DW fields of each message element of the respective TX Buffer). If you
require event logging for this message element, set the EFC bit in the DLC field.
b. Enable interrupt generation as required.
c. Set corresponding TRR bit(s) to enable buffer ready requests. The Host can enable
many transmission requests in one write to the TRR register.
CAN FD v2.0
PG223 December 5, 2018
If the CEN bit is cleared during core operation, Xilinx recommends resetting the core
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Chapter 3: Designing with the Core
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