Xilinx CAN FD v2.0 Product Manual page 41

Table 2-28: RX FIFO Status Register (Cont'd)
Bits Name
5:0 RI
Notes:
1. This register space is reserved for RX Mailbox buffer mode. Write has no effect and read returns 0.
RX FIFO Watermark Register (Address Offset + 00EC)
Table 2-29: RX FIFO Watermark Register
Bits Name
31:21 Reserved
20:16 RXFP
13:8 RXFWM_1
7:6 Reserved
CAN FD v2.0
PG223 December 5, 2018
Access Default
Value
RX FIFO-0 Read Index (0 to 63).
Each time IRI bit is set, core increments read index by + 1
(provided FILL level is not 0) and maintains it for Host to access
next available message.
• RI = 0x0 -> Next message read starts from location =
R 0
0x2100.
• RI = 0x1 -> Next message read starts from location =
0x2148.
RI is maintained if CEN bit is cleared.
RI gets reset to 0 if soft or hard reset is asserted.
Access Default
Value
– 0 Reserved.
Receive Filter Partition.
Received messages which match Filter-Mask pairs from 0 to RXFP
are stored in RX FIFO-0.
R/W 0x1f Received messages which match Filter-Mask pairs RXFP+1 and
above are stored into RX FIFO-1.
This field is available only when RX FIFO-1 is enabled.
Note:
This field can be changed when CEN = 0.
RX FIFO-1 Full Watermark.
This field is available only when RX FIFO-1 is enabled.
Note:
RX FIFO-1 generates FULL interrupt based on the value
programmed in this field. Set it within a 1-63 range.
R/W 0xf
The RX FIFO-1 Full Watermark interrupt in the ISR register
continues to assert as long as the RX FIFO-1 Fill Level is above
RX FIFO-1 Full watermark.
This field can be written to only when CEN bit in SRR is 0.
– 0 Reserved.
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Chapter 2: Product Specification
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