Xilinx CAN FD v2.0 Product Manual page 19

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Table 2-9: Error Counter Register
Bits Name
31:16 Reserved
15:8 REC[7:0]
7:0 TEC[7:0]
Error Status Register (Address Offset + 0x0014)
The Error Status register (ESR) indicates the type of error that has occurred on the bus. If
more than one error occurs, all relevant error flag bits are set in this register. The ESR is a
write 1 to clear register. Writes to this register do not set any bits, but clear the bits that are
set.
Table 2-10: Error Status Register
Bits Name
31:12 Reserved
11 F_BERR
10 F_STER
9 F_FMER
8 F_CRCER
7:5 Reserved
CAN FD v2.0
PG223 December 5, 2018
Default
Access
Value
– 0 Reserved.
Receive Error Count.
R 0
Indicates the value of Receive Error Counter.
Transmit Error Count.
R 0
Indicates the value of Transmit Error Counter.
Default
Value
0 Reserved
Bit Error in CAN FD Data Phase
• 1 = Indicates a bit error occurred in Data Phase (Fast) data rate.
0
• 0 = Indicates a bit error has not occurred in Data Phase (Fast) data rate
after the last write to this bit.
If this bit is set, writing a 1 clears it.
Stuff Error in CAN FD Data Phase.
• 1 = Indicates stuff error occurred in Data Phase (Fast) data rate.
0
• 0 = Indicates stuff error has not occurred in Data Phase (Fast) data rate.
after the last write to this bit.
If this bit is set, writing a 1 clears it.
Form Error in CAN FD Data Phase.
• 1 = Indicates form error occurred in Data Phase (Fast) data rate.
0
• 0 = Indicates form error has not occurred in Data Phase (Fast) data rate.
after the last write to this bit.
If this bit is set, writing a 1 clears it.
CRC Error in CAN FD Data Phase.
• 1 = Indicates CRC error occurred in Data Phase (Fast) data rate.
0
• 0 = Indicates CRC error has not occurred in Data Phase (Fast) data rate
after the last write to this bit.
If this bit is set, writing a 1 clears it.
0 Reserved.
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Chapter 2: Product Specification
Description
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