Xilinx CAN FD v2.0 Product Manual page 36

RX Buffer Control Status Register 2 (Address Offset + 0x00B8) (32 to 48 RX
Mailbox Buffers)
Description similar as
This register space is reserved for RX Sequential/FIFO mode or when the number of RX
Note:
mailbox buffers is 16/32. When reserved, write has no effect and read returns 0.
Interrupt Enable RX Buffer Full Register 0 (Address Offset + 0x00C0)
Table 2-25: Interrupt Enable RX Buffer Full Register 0
Bits Name
31:16 ERBF31/ERBF16
15 ERBF15
14 ERBF14
13 ERBF13
12 ERBF12
11 ERBF11
10 ERBF10
9 ERBF9
8 ERBF8
7 ERBF7
6 ERBF6
5 ERBF5
4 ERBF4
3 ERBF3
2 ERBF2
1 ERBF1
0 ERBF0
Notes:
1. This register space is reserved for RX sequential/FIFO buffer mode. Write has no effect and read returns 0.
Interrupt Enable RX Buffer Full Register 1 (Address Offset + 0x00C4)
Table 2-26: Interrupt Enable RX Buffer Full Register 1
Bits Name
31:16 Reserved
15:1 ERBF47/ERBF33
CAN FD v2.0
PG223 December 5, 2018
Table 2-24, page 35.
Default
Access
Value
R/W 0
These bits exist based on the number of RX buffers.
Note:
RX Buffer_15/1 Full Interrupt Enable
Description same as ERBF0.
RX Buffer_0 Full Interrupt Enable is for ERBF0.
R/W 0
• 1 = Enables setting RXBFL bit in the ISR when RX Buffer 0
becomes Full.
• 0 = RXBFL bit in the ISR does not set if RX Buffer 0
becomes Full.
Default
Access
Value
– 0 Reserved
RX Buffer_47/33 Full Interrupt Enable
R/W 0
Description same as ERBF32.
www.xilinx.com
Chapter 2: Product Specification
Description
Description
Send Feedback
36