Xilinx CAN FD v2.0 Product Manual page 27

Table 2-13: Interrupt Enable Register (Cont'd)
Bits Name
5 ETSCNT_OFLW
4 ERXOK
3 EBSFRD
2 EPEE
1 ETXOK
0 EARBLOST
Interrupt Clear Register (Address Offset + 0x0024)
The Interrupt Clear register (ICR) is used to clear interrupt status bits in the ISR register.
Table 2-14: Interrupt Clear Register
Bits Name
31 CTXEWMFLL
30 CTXEOFLW
17 CRXMNF
CRXBOFLW/
16
CRXFWMFLL_1
CAN FD v2.0
PG223 December 5, 2018
Access Default
Value
Timestamp Counter Overflow Interrupt Enable.
R/W 0
• 1 = Enables interrupt generation if TSCNT_OFLW bit in the ISR is set.
• 0 = Disables interrupt generation if TSCNT_OFLW bit in the ISR is set.
New Message Received Interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if RXOK bit in the ISR is set.
• 0 = Disables interrupt generation if RXOK bit in the ISR is set.
Bus-Off Recovery Done Interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if BSFRD bit in the ISR is set.
• 0 = Disables interrupt generation if BSFRD bit in the ISR is set.
Protocol Exception Event Interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if PEE bit in the ISR is set.
• 0 = Disables interrupt generation if PEE bit in the ISR is set.
Transmission Successful Interrupt Enable.
R/W 0 • 1 = Enables interrupt generation if TXOK bit in the ISR is set.
• 0 = Disables interrupt generation if TXOK bit in the ISR is set.
Arbitration Lost Interrupt Enable
R/W 0 • 1 = Enables interrupt generation if ARBLST bit in the ISR is set.
• 0 = Disables interrupt generation if ARBLST bit in the ISR is set.
Default
Access
Value
• 1 = Clears TX Event FIFO Watermark Full interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears TX Event FIFO Overflow interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears RX Match Not Finished interrupt status bit.
W 0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears RX Buffer Overflow interrupt status bit (Mailbox mode).
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
W 0
• 1 = Clears RX FIFO-1 Watermark Full interrupt status bit
(Sequential/FIFO Mode).
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
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Chapter 2: Product Specification
Description
Description
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