Xilinx CAN FD v2.0 Product Manual page 39

Table 2-27: Acceptance Filter (Control) Register (Cont'd)
Bits Name
7 UAF7
6 UAF6
5 UAF5
4 UAF4
3 UAF3
2 UAF2
1 UAF1
0 UAF0
Notes:
1. This register space is reserved for RX Mailbox buffer mode. Write has no effect and read returns 0.
RX FIFO Status Register (Address Offset + 0x00E8)
Table 2-28: RX FIFO Status Register
Bits Name
31 Reserved
30:24 FL_1[6:0]
CAN FD v2.0
PG223 December 5, 2018
Access Default
Value
Use Acceptance Filter Mask Pair 7.
R/W 0
Description same as UAF0.
Use Acceptance Filter Mask Pair 6.
R/W 0
Description same as UAF0.
Use Acceptance Filter Mask Pair 5.
R/W 0
Description same as UAF0.
Use Acceptance Filter Mask Pair 4.
R/W 0
Description same as UAF0.
Use Acceptance Filter Mask Pair 3.
R/W 0
Description same as UAF0.
Use Acceptance Filter Mask Pair 2.
R/W 0
Description same as UAF0.
Use Acceptance Filter Mask Pair 1.
R/W 0
Description same as UAF0.
Use Acceptance Filter Mask Pair 0.
Enables the use of acceptance filter mask pair 0.
• 1 = Indicates Acceptance Filter Mask register 0 (AFMR0 or
R/W 0
M0) and Acceptance Filter ID register 0 (AFID0 or F0) pair is
used for acceptance filtering.
• 0 = Indicates AFMR0 and AFID0 pair is not used for
acceptance filtering.
Access Default
Value
– 0 Reserved.
RX FIFO-1 Fill Level (0-64).
This field is reserved if RX FIFO-1 is not enabled.
Note:
Number of stored messages in RX FIFO-1 starting from the
read index (RI) given in this register.
R 0
For example, if FL = 0x5 and RI = 0x2 then RX FIFO-1 has five
messages starting from Read Index 2 (Start address 0x4190).
FL is maintained if CEN bit is cleared.
FL gets reset to 0 if soft or hard reset is asserted.
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Chapter 2: Product Specification
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