Chapter 5: Example Design; Overview - Xilinx CAN FD v2.0 Product Manual

Logicore ip
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Example Design

Overview

This chapter contains information about the example design provided in the Vivado
Design Suite environment. The top module instantiates all components of the core and
example design that are needed to implement the design in hardware, as shown in
Figure
5-1. This includes clock generator, traffic generator, and checker modules.
X-Ref Target - Figure 5-1
Clock Generator
This example design includes the following modules:
Clock Generator – The clocking wizard is used to generate two clocks, one for the
register interface (AXI4-Lite) and the other for the CAN FD clock.
Driver/Checker – An AXI4 traffic generator in system test mode is used to configure
the DUT and PARTNER to program and to check the status.
CAN FD Partner – The CAN FD IP in default mode to transmit and receive the packets
to and from DUT.
CAN FD v2.0
PG223 December 5, 2018
Driver/Checker
Figure 5-1: Example Design
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Chapter 5
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DUT
CAN FD
Partner
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