Xilinx CAN FD v2.0 Product Manual page 30

Table 2-16: Data Phase Baud Rate Prescaler Register (Cont'd)
Access Default
Bits Name
13:8 TDCOFF[5:0] R/W
7:0 DP_BRP[7:0] R/W
The following boundary conditions are imposed on sum of measured loop delay and TDC
IMPORTANT:
Offset:
Measured loop delay + TDCOFF < 3 bit times in the data phase
Ensure that the boundary condition is respected while programming the offset and data
phase bit rate. In case this sum exceeds 127 CAN clock periods, the maximum value of 127
CAN clock periods is used by the core for transmitter delay compensation.
If loop delay is < 1 data phase bit time, then TDC/SSP method is not needed.
Note:
Data Phase Bit Timing Register (Address Offset + 0x008C)
Table 2-17: Data Phase Bit Timing Register
Access Default
Bits Name
31:20 Reserved
19:16 DP_SJW[3:0] R/W
15:12 Reserved
11:8 DP_TS2[3:0] R/W
CAN FD v2.0
PG223 December 5, 2018
Value
Transmitter Delay Compensation Offset
This offset is specified in CAN clock cycles and is added to the measured
transmitter delay to place the Secondary Sample Point (SSP) at
0
appropriate position (for example, set this to half data bit time in terms
of CAN clock cycles to place SSP in the middle of the data bit).
This bit can be written only when CEN bit in SRR is 0.
Data Phase Baud Rate Prescaler
These bits indicate the prescaler value for Data Bit Timing as specified
in the CAN FD standard.
0
The actual value is one more than the value written to the register.
This bit can be written only when CEN bit in SRR is 0.
Value
– 0 Reserved
Data Phase Synchronization Jump Width
Indicates the Synchronization Jump Width as specified in the CAN FD
standard for Data Bit Timing.
0
The actual value is one more than the value written to the register.
This bit can be written only when CEN bit in SRR is 0.
– 0 Reserved
Data Phase Time Segment 2
Indicates the Phase Segment 2 as specified in the CAN FD standard for
Data Bit Timing.
0
The actual value is one more than the value written to the register.
This bit can be written only when CEN bit in SRR is 0.
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Chapter 2: Product Specification
Description
Description
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