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Status Register (Address Offset + 0x0018)
Table 2-11: Status Register
Bits
Name
31:21
Reserved
22:16
TDCV[6:0]
15:13
Reserved
12
SNOOP
11
Reserved
10
BSFR_CONFIG
9
PEE_CONFIG
8:7
ESTAT[1:0]
6
ERRWRN
5
BBSY
CAN FD v2.0
PG223 December 5, 2018
Default
Access
Value
–
0
Reserved.
Transmitter Delay Compensation Value.
This field gives the position of secondary sample point
R
0
(defined as sum of TDCOFF and measured delay for FDF to
res bit falling edge from TX to RX in CAN FD frame) in CAN
clocks. This field is for status purposes.
–
0
Reserved.
Snoop Mode.
R
0
• 1 = Indicates controller is in Snoop mode provided
Normal mode bit is also set in this register.
–
0
Reserved.
Bus-Off Recovery Mode Indicator.
• 1 = Indicates the core is in Bus-Off Recovery mode (Bus
R
0
Integration State).
When this bit is set, the BBSY and NORMAL status bits in
this register do not mean anything.
PEE Mode Indicator.
• 1 = Indicates the core is in PEE mode (Bus Integration
R
0
State).
When this bit is set, the BBSY and NORMAL status bits in
this register do not mean anything.
Error Status.
Indicates the error status of the core.
• 00 = Indicates Configuration mode (CONFIG = 1). Error
state is undefined.
R
0
• 01 = Indicates error active state.
• 11 = Indicates error passive state.
• 10 = Indicates Bus-Off state.
Error Warning.
Indicates that either the Transmit Error counter or the
Receive Error counter has exceeded a value of 96.
R
0
• 1 = one or more error counters have a value of 96.
• 0 = neither of the error counters has a value of 96.
Indicates the CAN bus status.
• 1 = Indicates that the core is either receiving a message
R
0
or transmitting a message.
• 0 = Indicates that the core is either in Configuration
mode or the bus is idle.
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Chapter 2: Product Specification
Description
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