Xilinx CAN FD v2.0 Product Manual page 40

Table 2-28: RX FIFO Status Register (Cont'd)
Bits Name
23 IRI_1
22 Reserved
21:16 RI_1[5:0]
15 Reserved
14:8 FL[6:0]
7 IRI
6 Reserved
CAN FD v2.0
PG223 December 5, 2018
Access Default
Value
RX FIFO-1 Increment Read Index by 1.
This field is reserved if RX FIFO-1 is not enabled.
Note:
With each Host writes setting this bit as 1, core increments the
Read Index (RI) field by 1 and updates the fill level (that is,
W 0
decrements it by 1). If the FILL level is 0, setting this bit has no
effect. The FILL level might remain unchanged when IRI is
written if the core is finishing a successful receive and is
incrementing the internal write index.
This bit always read as 0.
– 0 Reserved.
RX FIFO-1 Read Index (0 to 63).
This field is reserved if RX FIFO-1 is not enabled.
Note:
Each time the IRI bit is set, the core increments the read index
by + 1 (provided FILL level is not 0) and maintains it for Host
to access next available message.
R 0 • RI = 0x0 -> Next message read starts from location =
0x4100.
• RI = 0x1 -> Next message read starts from location =
0x4148.
RI is maintained if CEN bit is cleared.
RI gets reset to 0 if soft or hard reset is asserted.
– 0 Reserved.
RX FIFO-1 Fill Level (0 to 64).
The number of stored messages in Receive FIFO 0 starting
from the RI (Read Index) is given in this register.
R 0 For example, if FL = 0x5 and RI = 0x2, then RX FIFO-0 has five
messages starting from Read Index 2 (Start address 0x4190).
FL is maintained if CEN bit is cleared.
FL is reset to 0 if a soft or hard reset is asserted.
RX FIFO-0 Increment Read Index by 1.
With each Host writes setting this bit as 1, the core increments
the Read Index (RI field) by 1 and updates fill level (that is,
decrement by 1).
W 0
If FILL level is 0, setting this bit has no effect. The FILL level
might remain unchanged when IRI is written if core is just
finishing a successful receive and incrementing internal write
index.
This bit always read as 0.
– 0 Reserved.
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Chapter 2: Product Specification
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