Xilinx CAN FD v2.0 Product Manual page 47

Table 2-32: TB DLC Register (Cont'd)
Bits Name
23:16 MM
15:0 Reserved
TB*-DW0 Register (Address Offset + 0x0108,..., 0x0150,...)
Table 2-33: TB DW0 Register
Bits Name
31:24 Data bytes0 [7:0]
23:16 Data bytes1 [7:0]
15:8 Data bytes2 [7:0]
7:0 Data bytes3 [7:0]
Notes:
1. Only required DW locations needs to be written as per FDF and DLC field for a given message.
TB*-DW1-15 Register (Address Offset + 0x010C ..., 0x0154,...)
Description similar to
Only required DW locations needs to be written as per FDF and DLC field for a given message.
Note:
TX Event FIFO Status Register
CAN FD TX Event FIFO Register Descriptions
Table 2-34: CAN FD TXE Message Space
Start
Address
0x2000
0x2004
0x2008
CAN FD v2.0
PG223 December 5, 2018
Control/ Default
Status Value
Control N/A
N/A N/A
Default
Value
Data Byte 0.
N/A
Data byte needs to be transmitted with CAN or CAN FD frame
based on the DLC control field.
Data Byte 1.
N/A
Data byte needs to be transmitted with CAN or CAN FD frame
based on the DLC control field.
Data Byte 2.
N/A
Data byte needs to be transmitted with CAN or CAN FD frame
based on the DLC control field.
Data Byte 3.
N/A
Data byte needs to be transmitted with CAN or CAN FD frame
based on the DLC control field.
Table 2-33, page
Name
TXE FIFO TB0-ID
TXE FIFO TB0-DLC
TXE FIFO TB1-ID
www.xilinx.com
Description
Written by CPU during TX Buffer configuration. Copied into
Tx Event FIFO element for identification of TX message
status.
Reserved. Write to this field should be 0.
Description
47.
Access
Read Only TXE FIFO TB ID Register
Read Only TXE FIFO TB DLC Register
Read Only TXE FIFO TB ID Register
Chapter 2: Product Specification
Description
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