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16.1.1
Block Diagram
Figure 16.1 shows a block diagram of the on-chip RAM.
Legend:
SYSCR: System control register
Note: * The lower 20 bits of the address are shown.
16.1.2
Register Configuration
The on-chip RAM is controlled by SYSCR. Table 16.2 gives the address and initial value of
SYSCR.
Table 16.2 System Control Register
Address*
Name
H'EE012
System control register
Note: * Lower 20 bits of the address in advanced mode.
426
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Bus interface
H'FEF20*
H'FEF22*
On-chip RAM
H'FFF1E*
Even addresses
Figure 16.1 RAM Block Diagram
H'FEF21*
H'FEF23*
H'FFF1F*
Odd addresses
Abbreviation
R/W
SYSCR
R/W
SYSCR
Initial Value
H'09
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