Table of Contents
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Table 1.1
Features
Feature
Description
CPU
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
•
High-speed operation
•
•
•
16-Mbyte address space
Instruction features
•
•
•
•
Bit manipulation instructions with register-indirect specification of bit positions
Memory
H8/3008
•
•
Interrupt
controller
•
•
•
Bus controller
•
•
•
•
•
•
•
2
Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight
32-bit registers)
Maximum clock rate: 25 MHz
Add/subtract: 80 ns
Multiply/divide: 560 ns
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
Bit accumulator function
RAM: 4 kbytes
Seven external interrupt pins: NMI, IRQ
27 internal interrupts
Three selectable interrupt priority levels
Address space can be partitioned into eight areas, with independent bus
specifications in each area
Chip select output available for areas 0 to 7
8-bit access or 16-bit access selectable for each area
Two-state or three-state access selectable for each area
Selection of two wait modes
Number of program wait states selectable for each area
Bus arbitration function
Two address update modes
to IRQ
0
5
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