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5.2.1
System Control Register (SYSCR) ....................................................................... 75
5.2.2
Interrupt Priority Registers A and B (IPRA, IPRB).............................................. 76
5.2.3
IRQ Status Register (ISR) ..................................................................................... 81
5.2.4
IRQ Enable Register (IER) ................................................................................... 82
5.2.5
IRQ Sense Control Register (ISCR)...................................................................... 83
5.3
Interrupt Sources ................................................................................................................ 84
5.3.1
External Interrupts................................................................................................. 84
5.3.2
Internal Interrupts.................................................................................................. 85
5.3.3
Interrupt Exception Handling Vector Table.......................................................... 85
5.4
Interrupt Operation ............................................................................................................. 89
5.4.1
Interrupt Handling Process.................................................................................... 89
5.4.2
Interrupt Exception Handling Sequence ............................................................... 94
5.4.3
Interrupt Response Time ....................................................................................... 95
5.5
Usage Notes........................................................................................................................ 96
5.5.1
Contention between Interrupt and Interrupt-Disabling Instruction....................... 96
5.5.2
Instructions that Inhibit Interrupts......................................................................... 97
5.5.3
Interrupts during EEPMOV Instruction Execution ............................................... 97
6.1
Overview ............................................................................................................................ 99
6.1.1
Features ................................................................................................................. 99
6.1.2
Block Diagram ...................................................................................................... 100
6.1.3
Pin Configuration .................................................................................................. 101
6.1.4
Register Configuration .......................................................................................... 102
6.2
Register Descriptions.......................................................................................................... 102
6.2.1
Bus Width Control Register (ABWCR)................................................................ 102
6.2.2
Access State Control Register (ASTCR) .............................................................. 103
6.2.3
Wait Control Registers H and L (WCRH, WCRL) .............................................. 104
6.2.4
Bus Release Control Register (BRCR) ................................................................. 108
6.2.5
Bus Control Register (BCR) ................................................................................. 109
6.2.6
Chip Select Control Register (CSCR)................................................................... 111
6.2.7
Address Control Register (ADRCR)..................................................................... 112
6.3 Operation ................................................................................................................................. 113
6.3.1
Area Division ........................................................................................................ 113
6.3.2
Bus Specifications ................................................................................................. 115
6.3.3
Memory Interfaces ................................................................................................ 116
6.3.4
Chip Select Signals................................................................................................ 116
6.3.5
Address Output Method ........................................................................................ 117
6.4
Basic Bus Interface............................................................................................................. 119
6.4.1
Overview ............................................................................................................... 119
6.4.2
Data Size and Data Alignment.............................................................................. 119
6.4.3
Valid Strobes........................................................................................................ 120
6.4.4
Memory Areas....................................................................................................... 121
..................................................................................................... 99
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