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Table 12.8 SMR Settings and Serial Communication Formats
SMR Settings
Bit 7
Bit 6
Bit 2
C/A
CHR
MP
0
0
0
1
0
1
1
1
—
—
Table 12.9 SMR and SCR Settings and SCI Clock Source Selection
SMR
SCR Setting
Bit 7
Bit 1
Bit 0
C/A
CKE1
CKE0 Mode
0
0
0
1
1
0
1
1
0
0
1
1
0
1
340
Bit 5
Bit 3
PE
STOP
Mode
0
0
Asyn-
chronous
1
mode
1
0
1
0
0
1
1
0
1
—
0
Asyn-
chronous
mode (multi-
—
1
processor
—
0
format)
—
1
—
—
Syn-
chronous
mode
SCI Transmit/Receive clock
Clock Source SCK Pin Function
Asynchronous
Internal
mode
External
Synchronous
Internal
mode
External
SCI Communication Format
Multi-
pro-
Data
cessor
Length
Bit
8-bit data
Absent
7-bit data
8-bit data
Present
7-bit data
8-bit data
Absent
SCI does not use the SCK pin
Outputs clock with frequency matching the
bit rate
Inputs clock with frequency 16 times the bit
rate
Outputs the serial clock
Inputs the serial clock
Parity
Stop Bit
Bit
Length
Absent
1 bit
2 bits
Present
1 bit
2 bits
Absent
1 bit
2 bits
Present
1 bit
2 bits
Absent
1 bit
2 bits
1 bit
2 bits
None
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