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Read access
Write access
Note: n = 7 to 0
Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)
128
φ
Address bus
CS
n
AS
RD
D
to D
15
8
D
to D
7
0
HWR
LWR
D
to D
15
8
D
to D
7
0
(Byte Access to Odd Address)
Bus cycle
T
1
Odd external address in area n
High
Undetermined data
Valid
T
2
Invalid
Valid
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