Hitachi H8/3008 Hardware Manual page 274

16-bit microcomputer
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16-Bit Count Mode
• Channels 0 and 1:
When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit
timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
 Setting when Compare Match Occurs
• The CMFA or CMFB flag is set to 1 in 8TCSR0 when a 16-bit compare match occurs.
• The CMFA or CMFB flag is set to 1 in 8TCSR1 when a lower 8-bit compare match
occurs.
• TMO
pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR0 is in
0
accordance with the 16-bit compare match conditions.
• TMIO
pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR1 is in
1
accordance with the lower 8-bit compare match conditions.
 Setting when Input Capture Occurs
• The CMFB flag is set to 1 in 8TCSR0 and 8TCSR1 when the ICE bit is 1 in TCSR1
and input capture occurs.
• TMIO
pin input capture input signal edge detection is selected by bits OIS3 and OIS2
1
in 8TCSR0.
 Counter Clear Specification
• If counter clear on compare match or input capture has been selected by the CCLR1 and
CCLR0 bits in 8TCR0, the 16-bit counter (both 8TCNT0 and 8TCNT1) is cleared.
• The settings of the CCLR1 and CCLR0 bits in 8TCR1 are ignored. The lower 8 bits
cannot be cleared independently.
 OVF Flag Operation
• The OVF flag is set to 1 in 8TCSR0 when the 16-bit counter (8TCNT0 and 8TCNT1)
overflows (from H'FFFF to H'0000).
• The OVF flag is set to 1 in 8TCSR1 when the 8-bit counter (8TCNT1) overflows (from
H'FF to H'00).
• Channels 2 and 3:
When bits CKS2 to CKS0 are set to (100) in 8TCR2, the timer functions as a single 16-bit
timer with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits.
 Setting when Compare Match Occurs
• The CMFA or CMFB flag is set to 1 in 8TCSR2 when a 16-bit compare match occurs.
• The CMFA or CMFB flag is set to 1 in 8TCSR3 when a lower 8-bit compare match
occurs.
• TMO
pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR2 is in
2
accordance with the 16-bit compare match conditions.
• TMIO
pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR3 is in
3
accordance with the lower 8-bit compare match conditions.
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