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Address bus
CS
AS
RD
D
to D
Read access
15
D
to D
7
HWR
LWR
Write access
D
to D
15
D
to D
7
Note: n = 7 to 0
Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
T
1
Odd external address in area n
n
8
0
High
8
0
(Byte Access to Odd Address)
Bus cycle
T
T
2
Invalid
Valid
Undetermined data
Valid
3
125
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