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14.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t
after the ADST bit is set to 1, then starts conversion. Figure 14.5 shows the A/D
D
conversion timing. Table 14.4 indicates the A/D conversion time.
As indicated in figure 14.5, the A/D conversion time includes t
length of t
varies depending on the timing of the write access to ADCSR. The total conversion
D
time therefore varies within the ranges indicated in table 14.4.
In scan mode, the values given in table 14.4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 128 states when CKS = 0 or 66 states when
CKS = 1.
(1)
φ
Address bus
Write signal
Input sampling
timing
ADF
Legend:
ADCSR write cycle
(1):
ADCSR address
(2):
Synchronization delay
t :
D
Input sampling time
t
:
SPL
A/D conversion time
t
:
CONV
410
(2)
t
t
D
SPL
Figure 14.5 A/D Conversion Timing
and the input sampling time. The
D
t
CONV
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