Hitachi H8/3008 Hardware Manual page 296

Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5
and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits
7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1.
Address H'FFFA5
Bit
NDR7
Initial value
Read/Write R/W
Address H'FFFA7
Bit
—
Initial value
Read/Write —
280
7 6
NDR6 NDR5
0 0
R/W R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
7 6
— —
1 1
— —
Reserved bits
5 4
NDR4
0 0
R/W
5 4
— NDR3
1 1
— R/W
3 2
— —
1 1
— —
Reserved bits
3 2
NDR2 NDR1
0 0
R/W R/W
Next data 3 to 0
These bits store the next output
data for TPC output group 0
1 0
— —
1 1
— —
1 0
NDR0
0 0
R/W