Hitachi H8/3008 Hardware Manual page 418

ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7
ADF Description
0 [Clearing condition]
Read ADF when ADF =1, then write 0 in ADF.
1 [Setting conditions]
•
Single mode: A/D conversion ends
•
Scan mode: A/D conversion ends in all selected channels
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion.
Bit 6
ADIE Description
0 A/D end interrupt request (ADI) is disabled
1 A/D end interrupt request (ADI) is enabled
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin, or by an 8-bit
timer compare match.
Bit 5
ADST Description
0 A/D conversion is stopped
1 Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends.
Scan mode: A/D conversion starts and continues, cycling among the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a transition to
standby mode.
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on
operation in these modes, see section 14.4, Operation. Clear the ADST bit to 0 before switching
the conversion mode.
Bit 4
SCAN Description
0 Single mode
1 Scan mode
402
(Initial value)
(Initial value)
(Initial value)
(Initial value)