Hitachi H8/3008 Hardware Manual page 261

Bit 2 Bit 1
CSK2 CSK1
0 0
1
1 0
1
Notes: 1. If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is the
8TCNT0 compare match signal, no incrementing clock is generated. Do not use this
setting.
2. If the clock input of channel 2 is the 8TCNT3 overflow signal and that of channel 3 is the
8TCNT2 compare match signal, no incrementing clock is generated. Do not use this
setting.
Bit 0
CSK0 Description
0 Clock input disabled
Internal clock, counted on falling edge of φ/8
1
Internal clock, counted on falling edge of φ/64
0
Internal clock, counted on falling edge of φ/8192
1
0 Channel 0 (16-bit count mode): Count on 8TCNT1 overflow
1
signal*
Channel 1 (compare match count mode): Count on 8TCNT0
compare match A*
Channel 2 (16-bit count mode): Count on 8TCNT3 overflow
2
signal*
Channel 3 (compare match count mode): Count on 8TCNT2
compare match A*
1 External clock, counted on rising edge
0 External clock, counted on falling edge
1 External clock, counted on both rising and falling edges
1
2
(Initial value)
245