Hitachi H8/3008 Hardware Manual page 449

Table 17.3 Clock Timing (Preliminary)
Item
External clock input low
pulse width
External clock input high
pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
External clock output
settling delay time
includes a RES pulse width (t
Note: * t
DEXT
EXTAL
V = 3.0 V
CC
to 5.5 V
Symbol Min Max
t 30 —
EXL
t 30 —
EXH
t — 8
EXr
t — 8
EXf
t 0.4 0.6
CL
80 —
t 0.4 0.6
CH
80 —
t * 500 —
DEXT
). t
RESW
t
EXH
t
EXr
Figure 17.6 External Clock Input Timing
V = 5.0 V
CC
± 10%
Min Max
15 —
15 —
— 5
— 5
0.4 0.6
80 —
0.4 0.6
80 —
500 —
= 20 t
RESW cyc
t
EXL
× 0.7
V
CC
0.3 V
t
EXf
Unit Test Conditions
ns Figure 17.6
ns
ns
ns
φ ≥ 5 MHz Figure
t
cyc
19.17
φ < 5 MHz
ns
φ ≥ 5 MHz
t
cyc
φ < 5 MHz
ns
µs Figure 17.7
× 0.5
V
CC
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