Hitachi H8/3008 Hardware Manual page 369

In transmitting serial data, the SCI operates as follows:
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
 Start bit: One 0 bit is output.
 Transmit data: 7 or 8 bits are output, LSB first.
 Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
 Stop bit(s): One or two 1 bits (stop bits) are output.
 Mark state: Output of 1 bits continues until the start bit of the next transmit data.
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop
bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time
Figure 12.11 shows an example of SCI transmit operation using a multiprocessor format.
Start
bit
1
D0
0
TDRE
TEND
TXI interrupt handler
TXI interrupt
writes data in TDR and
request
clears TDRE flag to 0
• Receiving Multiprocessor Serial Data: Figure 12.12 shows a sample flowchart for receiving
multiprocessor serial data and indicates the procedure to follow.
Multi-
processor
Data
D1 D7
TXI interrupt
request
1 frame
Figure 12.11 Example of SCI Transmit Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
Stop
Start
bit bit bit
0/1 1 0 D0
Multi-
processor
Data
bit
D1 D7 0/1
Stop
bit
1
Idle (mark)
state
TEI interrupt
request
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