Hitachi H8/3008 Hardware Manual page 362

In transmitting serial data, the SCI operates as follows:
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
 Start bit: One 0 bit is output.
 Transmit data: 7 or 8 bits are output, LSB first.
 Parity bit or multiprocessor bit: One parity bit (even or odd parity),or one multiprocessor
bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can
also be selected.
 Stop bit(s): One or two 1 bits (stop bits) are output.
 Mark state: Output of 1 bits continues until the start bit of the next transmit data.
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop
bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time
Figure 12.6 shows an example of SCI transmit operation in asynchronous mode.
1
Start bit
D0
0
TDRE
TEND
TXI interrupt TXI interrupt handler
request writes data in TDR and
clears TDRE flag to 0
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode
346
Parity
Data
bit
D1 D7 0/1
1 frame
TXI interrupt
request
(8-Bit Data with Parity and One Stop Bit)
Stop
Start
bit
bit
1 0 D0 D1
Parity Stop
Data
bit bit
D7 0/1 1
Idle state
(mark state)
TEI interrupt
request
1