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8TCSR0—Timer Control/Status Register 0
Bit
Initial value
Read/Write
Compare match/input capture flag B
Notes: 1. Only 0 can be written to bits 7 to 5 to clear these flags.
2. TRGE is bit 7 of the A/D control register (ADCR).
556
7
6
5
CMFB
CMFA
OVF
0
0
0
1
1
1
R/(W)*
R/(W)*
R/(W)*
A/D trigger enable
TRGE
Note: * TRGE is bit 7 of the A/D control register (ADCR).
Timer overflow flag
[Clearing condition]
0
Read OVF when OVF = 1, then write 0 in OVF.
[Setting condition]
1
8TCNT overflows from H'FF to H'00.
Compare match flag A
[Clearing condition]
0
Read CMFA when CMFA = 1, then write 0 in CMFA.
[Setting condition]
1
8TCNT = TCORA
[Clearing condition]
0
Read CMFB when CMFB = 1, then write 0 in CMFB.
[Setting conditions]
8TCNT = TCORB
1
• The 8TCNT value is transferred to TCORB by an input capture signal when
• TCORB functions as an input capture register.
H'FFF82
4
3
2
ADTE
OIS3
OIS2
0
0
0
R/W
R/W
R/W
Output select A1 and A0
Bit 1
Bit 0
OS1
OS0
0
0
1
0
1
1
Output/input capture edge select B3 and B2
ICE in
Bit 3
Bit 2
8TCSR1
OIS3
OIS2
0
0
1
0
0
1
1
0
0
1
1
0
1
1
Bit 4
2
*
Description
ADTE
A/D converter start requests by compare match
0
A or an external trigger are disabled
0
A/D converter start requests by compare match
1
A or an external trigger are disabled
A/D converter start requests by an external trigger are enabled, and
0
A/D converter start requests by compare match A are disabled
1
A/D converter start requests by compare match A are enabled, and
1
A/D converter start requests by an external trigger are disabled
8-bit timer channel 0
1
0
OS1
OS0
0
0
R/W
R/W
Description
No change at compare match A
0 output at compare match A
1 output at compare match A
Output toggles at compare
match A
Description
No change at compare match B
0 output at compare match B
1 output at compare match B
Output toggles at compare match
B
TCORB input capture on rising
edge
TCORB input capture on falling
edge
TCORB input capture on both
rising and falling edges
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