Hitachi H8/3008 Hardware Manual page 13

Section 15 D/A Converter
15.1 Overview ............................................................................................................................ 417
15.1.1 Features ................................................................................................................. 417
15.1.2 Block Diagram ...................................................................................................... 418
15.1.3 Pin Configuration .................................................................................................. 419
15.1.4 Register Configuration .......................................................................................... 419
15.2 Register Descriptions.......................................................................................................... 420
15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) .................................................. 420
15.2.2 D/A Control Register (DACR).............................................................................. 420
15.2.3 D/A Standby Control Register (DASTCR)........................................................... 422
15.3 Operation ............................................................................................................................ 422
15.4 D/A Output Control............................................................................................................ 424
Section 16 RAM
16.1 Overview ............................................................................................................................ 425
16.1.1 Block Diagram ...................................................................................................... 426
16.1.2 Register Configuration .......................................................................................... 426
16.2 System Control Register (SYSCR) .................................................................................... 427
16.3 Operation ............................................................................................................................ 428
Section 17 Clock Pulse Generator
17.1 Overview ............................................................................................................................ 429
17.1.1 Block Diagram ...................................................................................................... 429
17.2 Oscillator Circuit ................................................................................................................ 430
17.2.1 Connecting a Crystal Resonator............................................................................ 430
17.2.2 External Clock Input ............................................................................................. 432
17.3 Duty Adjustment Circuit .................................................................................................... 434
17.4 Prescalers............................................................................................................................ 434
17.5 Frequency Divider.............................................................................................................. 434
17.5.1 Register Configuration .......................................................................................... 435
17.5.2 Division Control Register (DIVCR) ..................................................................... 435
17.5.3 Usage Notes .......................................................................................................... 436
Section 18 Power-Down State
18.1 Overview ............................................................................................................................ 437
18.2 Register Configuration ....................................................................................................... 439
18.2.1 System Control Register (SYSCR) ....................................................................... 439
18.2.2 Module Standby Control Register H (MSTCRH)................................................. 440
18.2.3 Module Standby Control Register L (MSTCRL).................................................. 442
18.3 Sleep Mode......................................................................................................................... 444
18.3.1 Transition to Sleep Mode ...................................................................................... 444
18.3.2 Exit from Sleep Mode ........................................................................................... 444
18.4 Software Standby Mode ..................................................................................................... 444
.................................................................................................. 417
.................................................................................................................... 425
.......................................................................................... 437
................................................................................... 429
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