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Port A pins
PA /TP /TIOCB /A
7
PA /TP /TIOCA /A
6
PA /TP /TIOCB /A
5
PA /TP /TIOCA /A
4
Port A
PA /TP /TIOCB /TCLKD
3
PA /TP /TIOCA /TCLKC
2
PA /TP /TCLKB
1
PA /TP /TCLKA
0
7.7.2
Register Descriptions
Table 7.11 summarizes the registers of port A.
Table 7.11 Port A Registers
Address*
Name
H'EE009
Port A data direction
register
H'FFFD9
Port A data register
Note: * Lower 20 bits of the address in advanced mode.
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
Pin functions in modes 1 and 2
PA (input/output)/TP (output)/TIOCB (input/output)
7
2
20
PA (input/output)/TP (output)/TIOCA (input/output)
21
6
2
PA (input/output)/TP (output)/TIOCB (input/output)
5
1
22
PA (input/output)/TP (output)/TIOCA (input/output)
23
4
1
PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
3
0
PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)
2
0
PA (input/output)/TP (output)/TCLKB (input)
1
PA (input/output)/TP (output)/TCLKA (input)
0
Pin functions in modes 3 and 4
A
PA (input/output)/TP (output)/TIOCA (input/output)/A
PA (input/output)/TP (output)/TIOCB (input/output)/A
PA (input/output)/TP (output)/TIOCA (input/output)/A
PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)
PA (input/output)/TP (output)/TCLKB (input)
PA (input/output)/TP (output)/TCLKA (input)
Figure 7.6 Port A Pin Configuration
PADDR
PADR
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
(output)
20
6
6
5
5
4
4
3
3
2
2
1
1
0
0
R/W
Modes 1 and 2
W
H'00
R/W
H'00
2
2
1
1
0
0
(output)
2
21
(output)
1
22
(output)
1
23
0
0
Initial Value
Modes 3 and 4
H'80
H'00
157
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