Hitachi H8/3008 Hardware Manual page 538

Data
Address Register Bus
(Low) Name Width Bit 7
H'FFFE0 ADDRAH 8
H'FFFE1 ADDRAL 8
H'FFFE2 ADDRBH 8
H'FFFE3 ADDRBL 8
H'FFFE4 ADDRCH 8
H'FFFE5 ADDRCL 8
H'FFFE6 ADDRDH 8
H'FFFE7 ADDRDL 8
H'FFFE8 ADCSR 8
H'FFFE9 ADCR 8
Notes: 1. Writing to bits 5 to 2 of BCR is prohibited.
2. For the procedure for writing to TCSR, TCNT, and RSTCSR, see section 11.2.4, Notes
on Register Rewriting.
3. The address depends on the output trigger setting.
Legend:
WDT: Watchdog timer
TPC: Programmable timing pattern controller
SCI: Serial communication interface
522
Bit 6 Bit 5
AD9 AD8 AD7
AD1 AD0 —
AD9 AD8 AD7
AD1 AD0 —
AD9 AD8 AD7
AD1 AD0 —
AD9 AD8 AD7
AD1 AD0 —
ADF ADIE ADST
TRGE — —
Bit Names
Bit 4 Bit 3 Bit 2
AD6 AD5 AD4
— — —
AD6 AD5 AD4
— — —
AD6 AD5 AD4
— — —
AD6 AD5 AD4
— — —
SCAN CKS CH2
— — —
Bit 1 Bit 0 Module Name
AD3 AD2 A/D converter
— —
AD3 AD2
— —
AD3 AD2
— —
AD3 AD2
— —
CH1 CH0
— —