Hitachi H8/3008 Hardware Manual page 249

Table 8.7 (b) 16-bit timer Operating Modes (Channel 1)
Operating Mode
Synchronous preset
PWM mode
Output compare A
Output compare B
Input capture A
Input capture B
Counter By compare
clearing match/input
capture A
By compare
match/input
capture B
Syn-
chronous
clear
Legend: Setting available (valid). — Setting does not affect this mode.
Note: The input capture function cannot be used in PWM mode. If compare match A and compare match B
*
occur simultaneously, the compare match signal is inhibited.
TSNC
Synchro-
nization MDF
SYNC1 = 1 —
—
—
—
—
—
—
—
SYNC1 = 1 —
Register Settings
TMDR
FDIR PWM IOA
—
— PWM1 = 1 —
— PWM1 = 0 IOA2 = 0
Other bits
unrestricted
—
— PWM1 = 0 IOA2 = 1
Other bits
unrestricted
— PWM1 = 0
—
—
—
TIOR1
Clear
IOB Select
*
IOB2 = 0
Other bits
unrestricted
IOB2 = 1
Other bits
unrestricted
CCLR1 = 0
CCLR0 = 1
CCLR1 = 1
CCLR0 = 0
CCLR1 = 1
CCLR0 = 1
16TCR1
Clock
Select
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