Register Configuration; Division Control Register (Divcr) - Hitachi H8/3008 Hardware Manual

17.5.1

Register Configuration

Table 17.4 summarizes the frequency division register.
Table 17.4 Frequency Division Register
Address* Name
H'EE01B Division control register
Note: * Lower 20 bits of the address in advanced mode.
17.5.2

Division Control Register (DIVCR)

DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
Bit
Initial value
Read/Write
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.
Bits 1 and 0—Divide (DIV1, DIV0): These bits select the frequency division ratio, as follows.
Bit 1 Bit 0
DIV1 DIV0
0 0
0 1
1 0
1 1
7 6
— —
1 1
— —
Reserved bits
Frequency Division Ratio
1/1
1/2
1/4
1/8
Abbreviation
DIVCR
5 4
— —
1 1
— —
R/W Initial Value
R/W H'FC
3 2
— — DIV1
1 1
— — R/W
Divide bits 1 and 0
These bits select the
frequency division ratio
1 0
DIV0
0 0
R/W
(Initial value)
435